As is known by those of skill in the art, static random access memory (SRAM) integrated circuits may exhibit relatively low power consumption and high operating speeds as compared to dynamic random access memory (DRAM) integrated circuits. As a result, SRAM circuits are widely used to implement cache memories in computers and portable consumer electronic devices.
The unit cells of an SRAM integrated circuit can be implemented, for example, as either a high load resistor SRAM cell or as a complementary metal oxide semiconductor (CMOS)SRAM cell. Typically, the high load resistor SRAM cells use a high resistance resistor as the load device, and the CMOS SRAM cells use a p-channel or “p-type” metal oxide semiconductor (PMOS) transistor as the load device.
At least two types of CMOS SRAM unit cells are known in the art. The first type is a thin film transistor (TFT) SRAM cell in which thin film transistors are stacked on a semiconductor substrate as the load device. The second type of CMOS SRAM unit cell is a bulk CMOS SRAM cell that uses bulk transistors that are formed at a semiconductor substrate as the load device.
The bulk CMOS SRAM cells may exhibit high cell stability (i.e., good low voltage characteristics and low stand-by current) as compared to TFT SRAM cells and high-load resistor SRAM cells. This high degree of cell stability may be achieved because the bulk transistors in the bulk CMOS SRAM cell are formed at a single crystalline silicon substrate, whereas the thin film transistors of the TFT SRAM cells are typically formed using polysilicon layers. However, bulk CMOS SRAM cells may exhibit low integration density and/or weak latch-up immunity as compared to TFT SRAM cells.
Typically, each SRAM unit cell includes a pair of node contact structures. In the TFT SRAM cells, each of the node contact structures electrically connects a P-type drain region of the load transistor to an N-type drain region of a driver transistor. Typically, an ohmic contact is provided between the P-type drain region of the load transistor and the N-type drain region of the driver transistor.
Semiconductor devices that include TFTs stacked over a semiconductor substrate are disclosed in U.S. Pat. No. 6,022,766 to Chen et al., entitled “Semiconductor Structure Incorporating Thin Film Transistors and Methods for Its Manufacture.” In particular, Chen et al. discloses a semiconductor device in which a conventional bulk transistor is formed at a single crystalline silicon substrate, and a thin film transistor is then stacked over the bulk transistor. In Chen et al., the body layer of the TFT is formed by depositing an amorphous silicon layer on the semiconductor substrate and a metal plug. This amorphous silicon layer is then crystallized via a thermal treatment process. This thermal treatment process converts the amorphous silicon layer into a polycrystalline or “polysilicon” layer having large grains. The electrical characteristics of these TFTs that are formed with a polysilicon body layer may not be as good as the electrical characteristics of bulk transistors formed at a single crystalline silicon substrate.